1. Technical Field
The disclosed embodiments relate to de-interleaving, and more particularly to de-interleaving utilizing a multi-banked memory.
2. Background Information
FIG. 1 (Prior Art) is a simplified block diagram of one type of conventional wireless communication device 1 such as a cellular telephone. Wireless communication device 1 includes an antenna 2, an RF transceiver integrated circuit 3, and a digital baseband integrated circuit 4. The digital baseband integrated circuit 4 contains a modular transmit channel (TX) 5 and a modulator receive channel (RX) 6. If the device 1 is transmitting, then information 7 to be transmitted passes through the modulator transmit channel 5 which includes an encoder circuit 8, a mapper circuit 9, a modulator circuit 10, an Inverse Fast Fourier Transform (IFFT) circuit 11, and a windowing circuit 12. The information is converted into analog form by Digital-to-Analog Converter (DAC) 13, and passes through RF transceiver integrated circuit 3, for transmission from antenna 2. Because the information may be degraded during transmission by impairments such as thermal noise, interference, and spurious signals, the information is encoded and interleaved before transmission. Encoding and interleaving techniques are employed to allow a receiving wireless communication device to perform de-interleaving and decoding to recover degraded or impaired information.
The structure of a receiving wireless communication device that receives the transmission may be the same as the structure set forth in FIG. 1. The transmission is received on antenna 2, and passes through RF transceiver integrated circuit 3, is converted into digital form by an Analog-to-Digital Converter (ADC) 14, and passes through modular receive channel (RX) 6. Receive channel 6 includes a front end circuit 15, a Fast Fourier Transform (FFT) circuit 16, a demodulator circuit 17, a DEMAP circuit 18, a Log-Likelihood Ratio (LLR) buffer 19, and a decoder circuit 20. The DEMAP circuit 18 in turn includes unpaint circuit 21, an LLR generator circuit 22, a descrambler circuit 23, and a de-interleaver circuit 24. De-interleaver circuit 24 may, for example, receive a stream of interleaved LLR values, de-interleave the stream, and write the LLR values into buffer 19 in de-interleaved fashion. Decode circuit 20 reads the LLR values from buffer 19 and performs decoding on the values, thereby recovering the originally transmitted information represented by arrow 25. As data throughput requirements on such wireless communication devices increase, ever faster and more efficient de-interleaving methods and structures are required. Thus an improved de-interleaving process is desired.